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332BUGA1
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DEBUG MONITOR USER'S MANUAL MOTOROLA
C-1 M68332BUG
DEBUG MONITOR USER'S MANUAL MOTOROLA
M68332BUG C-1
DEBUG MONITOR USER'S MANUAL MOTOROLA
A-1 M68332BUG
DEBUG MONITOR USER'S MANUAL MOTOROLA
M68332BUG A-1
APPENDIX C
USER CUSTOMIZATION
INTRODUCTION
Within the 332Bug certain operating parameters may be customized for the user's particular
situation. This appendix details the customization features of 332Bug. An IBM-PC or
compatible host computer with the Motorola EVSbug332 software, BCCDI, and PFB are
required to reprogram the EPROM on the BCC. This appendix assumes the user is using the
ProComm terminal emulation program on the host computer to communicate with 332Bug
and is familiar with the following; 332Bug, ProComm, MS-DOS, and EVSbug332.
CAUTION
Failure to incorporate changes as specified may cause malfunctions in the
332Bug. Novices should not attempt to customize 332Bug.
The user customization area is the first 512 bytes of 332Bug ($60000-$601FF), see Table C-
1. For brevity's sake, all entries have been shown as an offset value from the $60000 base
address of 332Bug. The source code equivalent of the customization area is available on the
Motorola FREEWARE BBS at (512) 891-FREE, i.e.. (512) 891-3733 under the archive
filename 332BUG1.ARC. Future updates for 332Bug will also be available on the
FREEWARE BBS under the archive filename 332BUGxx.ARC. The EVSbug332 program is
also available on the FREEWARE BBS in the archive file EVSBUG332.ARC. The
FREEWARE line operates continuously except for maintenance periods and is set up for 300-
2400 baud, 8-bit, no parity, and 1 stop bit.
Because there are two versions of the M68332BCC, there are two sets of chip select tables;
one set for Rev. A and one set for Rev. B. 332Bug power-up initializes the common CSBOOT
chip select and CS0/CS1 (see Rev. A table values). 332Bug then tests for RAM at location
$0 to determine if the hardware is Rev. A or Rev. B. Chip select initialization then proceeds
using the values from the proper table. The only changes required by the user are to the
WAIT CYCLES or BASE ADDRESS fields for their platform board (PFB) sockets, or to use an
unused chip select.
332BUG CUSTOMIZATION
The general procedure for customizing 332Bug is as follows:
1. Copy the parameter area from the 332Bug EPROM to RAM by entering the
following command:
332Bug>BM 60000 601FF 4000<CR>
2. Modify the parameters in RAM using the offsets shown in Table C-1. For
example, the CHECKSUM value would begin at location $4000 plus offset
$0E, or $400E. Thus the word at $400E must be changed to $FFFF so a
new checksum value for the customized 332Bug can be calculated. Enter
the following command to change the CHECKSUM value.
332Bug>MS 400E FFFF<CR>
Change the SIGNON message to indicate customization has been
performed. Change the spaces after "Version 1.01" to read ".XX <title>",
where "XX" is your customized version number starting with 01 and <title> is
the name of your company or school/lab.
3. Create an S-record file of the changes on the host computer by entering the
ALT-F1 key on the host computer terminal (for ProComm emulator program)
to open a log file. Enter the file name 332BUG1.MX and then complete the
332Bug DU command by pressing <CR>. The offset of 5C000 is required to
create the S-records with the proper starting address of $60000 for
EVSbug332.
332Bug>DU 4000 41FF '332BUG1.MX' ,5C000<ALT-F1><CR>
4. Create an S-record file of the rest of 332Bug on the host computer by
entering the ALT-F1 key on the host computer terminal (for ProComm
emulator program) to open a log file. Enter the file name 332BUG23.MX
and then complete the 332Bug DU command by pressing <CR>.
332Bug>DU 60200 7FFFF '332BUG23.MX'<ALT-F1><CR>
5. If desired, the two S-record files can be edited on the host computer to
remove the "Effective address" lines at the beginning of the file and the
332Bug> prompt at the end, but it is not required. If the two S-record files
are concatenated into one file, edit the first file to remove the S8 termination
record at the end of the file.
6. Verify the customized S-record file, 332BUG1.MX, by entering the
command shown below. The -5C000 offset is required to relocate the
verification from the $60000 base address of the S-records to the RAM
change area at $4000.
332Bug>VE -5C000<CR>
Enter the terminal emulator's escape key to return to the host computer's
operating system (ALT-F4 for ProComm). Then enter the host command to
send the S-record file to the port where the BCC is connected (type
332bug1.mx >com1, when the BCC is connected to the com1 port).
After the file has been sent, restart the terminal emulation program by
entering EXIT on the host computer. Then enter two <CR>'s to signal the
332Bug that verification is complete and the terminal emulator program is
ready to receive the status message.
<CR><CR>
Verify passes.
332Bug>
7. Verify the main S-record file, 332BUG23.MX, by entering the command
shown below. No offset is required.
332Bug>VE<CR>
Enter the terminal emulator's escape key to return to the host computer's
operating system (ALT-F4 for ProComm). Then enter the host computer
command to send the S-record file to the BCC (type 332bug23.mx
>com1, when the BCC is connected to the com1 port).
After the file has been sent, restart the terminal emulation by entering EXIT
on the host computer. Then enter two <CR>'s to signal the 332Bug that
verification is complete and the terminal emulator program is ready to
receive the status message.
<CR><CR>
Verify passes.
332Bug>
8. Follow the EVSbug332 directions for reprogramming the BCC EPROM using
the two S-record files, 332BUG1.MX and 332BUG23.MX.
9. Power up the newly programmed BCC and note the checksum value
indicated. Repeat steps 1 through 8 above, to set the checksum to this value
but with the changes noted below.
Ñ STEP 1: No change.
Ñ STEP 2: Change checksum to the value noted on power-up
per the command below where "XXXX" is the value
noted.
332Bug>MS 400E XXXX<CR>
Ñ STEP 3: Change the filename to 332BUG1C.MX. To speed
up reprogramming, a temporary file consisting of only
the checksum word could be used by entering DU
400E 400F 'TMP.MX' ,5C000<ALT-F1><CR>
after creating the 332BUG1C.MX file.
Ñ STEP 4: Skip this step.
Ñ STEP 5: No change.
Ñ STEP 6: No change.
Ñ STEP 7: This step is optional.
Ñ STEP 8: Only the checksum value needs to be programmed
using the indicated value. Since the checksum was
set to the unprogrammed state of the EPROM
($FFFF), programming can start immediately. DO
NOT ERASE THE BCC EPROM!
10. Power-up the BCC once again. The checksum message should not
appear.
11. On the host computer, enter the following commands to update the two
332Bug S-record files so they may be properly archived to a floppy disk for
safe keeping:
C>DEL TMP.MX<CR>
C>DEL 332BUG1.MX<CR>
C>RENAME 332BUG1C.MX 332BUG1.MX<CR>
C>COPY 332BUG*.MX A:<CR>
12. The customization procedure is now complete.
CUSTOMIZATION TABLE
Table C-1. 332Bug Customization Area
DEFAULT
OFFSET VALUE MNEMONIC DESCRIPTION
$00-03 $00002FFC PWR_SSP Power on/reset stack pointer
$04-07 $00060090 PWR_PC Power on/reset program counter
$08-0B $00020000 CODESIZE Size of 332Bug ROM in bytes:
Number of bytes for checksum calculation.
Must be an even number of bytes.
$0C-0D $FFFF CHECKALT Checksum alternate:
Change this if CHECKSUM should ever
be calculated as $FFFF.
$0E-0F $9F8F CHECKSUM Checksum value:
$FFFF = calculate new checksum value
else checksum has been set.
Old Chip Select Table (Rev. A BCC + Rev. A PFB)
$10-11 $0003 .CSBAR0 CS0 base address register value and
$12-13 $5830 .CSOR0 . option register value
$14-15 $0003 .CSBAR1 CS1 base address register value and
$16-17 $3830 .CSOR1 . option register value
$18-19 $0103 .CSBAR2 CS2 base address register value and
$1A-1B $6870 .CSOR2 . option register value
$1C-1D $0103 .CSBAR3 CS3 base address register value and
$1E-1F $3030 .CSOR3 . option register value
$20-21 $0804 .CSBAR4 CS4 base address register value and
$22-23 $5870 .CSOR4 . option register value
$24-25 $0804 .CSBAR5 CS5 base address register value and
$26-27 $3870 .CSOR5 . option register value
$28-29 $FFE8 .CSBAR6 CS6 base address register value and
$2A-2B $783F .CSOR6 . option register value
$2C-2D $0000 .CSBAR7 CS7 base address register value and
$2E-2F $0000 .CSOR7 . option register value
$30-31 $FFF8 .CSBAR8 CS8 base address register value and
$32-33 $680F .CSOR8 . option register value
$34-35 $0000 .CSBAR9 CS9 base address register value and
$36-37 $0000 .CSOR9 . option register value
$38-39 $0103 .CSBAR10 CS10 base address register value and
$3A-3B $5030 .CSOR10 . option register value
Table C-1. 332Bug Customization Area (cont'd)
DEFAULT
OFFSET VALUE MNEMONIC DESCRIPTION
Common Chip Select Table: (Rev. A BCC + Rev. A PFB) &
(Rev. B BCC + Rev. B PFB)
$3C-3D $0604 .CSBARBT CSBOOT base address register value and
$3E-3F $68B0 .CSORBT . option register value
New Chip Select Table: (Rev. B BCC + Rev. B PFB)
$40-41 $0003 CSBAR0$ CS0 base address register value and
$42-43 $503E CSOR0$ . option register value
$44-45 $0003 CSBAR1$ CS1 base address register value and
$46-47 $303E CSOR1$ . option register value
$48-49 $0003 CSBAR2$ CS2 base address register value and
$4A-4B $683E CSOR2$ . option register value
$4C-4D $0000 CSBAR3$ CS3 base address register value and
$4E-4F $0000 CSOR3$ . option register value
$50-51 $FFF8 CSBAR4$ CS4 base address register value and
$52-53 $680F CSOR4$ . option register value
$54-55 $FFE8 CSBAR5$ CS5 base address register value and
$56-57 $783F CSOR5$ . option register value
$58-59 $0804 CSBAR6$ CS6 base address register value and
$5A-5B $38F0 CSOR6$ . option register value
$5C-5D $0804 CSBAR7$ CS7 base address register value and
$5E-5F $58F0 CSOR7$ . option register value
$60-61 $0103 CSBAR8$ CS8 base address register value and
$62-63 $6870 CSOR8$ . option register value
$64-65 $0103 CSBAR9$ CS9 base address register value and
$66-67 $3030 CSOR9$ . option register value
$68-69 $0103 CSBAR10$ CS10 base address register value and
$6A-6B $5030 CSOR10$ . option register value
$6C-6F $FFFFFFFF <reserved>
Standby RAM Module
$70-71 $FFFF .RAMMCR RAM module configuration register value
$72-73 $FFFF .RAMBAR RAM array base address register value
Bit 0 = 1 disables RAM array initialization
= 0 enables RAM array initialization
Table C-1. 332Bug Customization Area (cont'd)
DEFAULT
OFFSET VALUE MNEMONIC DESCRIPTION
Periodic Interrupt Timer
$74-75 $0642 .PICR Periodic interrupt control register value:
Default value is set for level 6, vect. 66.
$76-77 $0102 .PITR Periodic interrupt timing register value:
Controls the "tick" time for the SYSCALL
timing functions ($4X). Default value is set
for 125 milliseconds.
ROM Auto Boot Vectors
$78-7B $FFFFFFFF RB_SP ROM auto boot stack pointer value
$7C-7F $FFFFFFFF RB_PC ROM auto boot program counter value:
Bit 0 = 1 disables auto boot (odd
address)
= 0 enables auto boot (even
address). Enabling is equivalent to
changing the stack pointer (SP) and
program counter (PC) and entering
the GO command.
Console Default Table for SCI (CONSCI)
$80-83 $00001C0F .PARMS Parameter definition for below:
Do not change this value.
$84-85 $2580 .BAUD Baud rate (in decimal):
19200 = $4B00
9600 = $2580
4800 = $12C0
2400 = $0960
1200 = $04B0
600 = $0258
300 = $012C
$86 $00 .PARITY Parity selection (see Table C-2):
None = $00
Even = $45 = 'E'
Odd = $4F = 'O'
$87 $08 .DATA Data bits (see Table C-2):
8-bits = $08
7-bits = $07
Table C-1. 332Bug Customization Area (cont'd)
DEFAULT
OFFSET VALUE MNEMONIC DESCRIPTION
Console Default Table for SCI (CONSCI) (cont'd)
$88 $01 .STOP Stop bits (see Table C-2):
1-bit = $01
2-bit = $02
$89 $FF .XON_ENB XON/XOFF enable:
enable = $FF
disable = $00
$8A $11 .XON XON character (7-bit ASCII):
^Q = $11
$8B $13 .XOFF XOFF character (7-bit ASCII):
^S = $13
$8C-8F $FFFFFFFF <reserved>
Power On Branch Vectors (PWR_XXX): no registers preserved
$90-95 $60FF0000E098 PWR_INI BRA.L to MCU initialization routine:
Returns to PWR_TTL (no stack usage!).
$96-9B $60FF00000004 PWR_TTL BRA.L to title printing routine:
Returns to PWR_TST (no stack usage!).
$9C-A1 $60FF0000DD26 PWR_TST BRA.L to self-test routine:
Returns to PWR_GO (no stack usage!).
$A2-A7 $60FF0000D93C PWR_GO BRA.L to 332Bug start up routine:
Never returns.
$A8-AD all $FF's BRA.L <reserved>
$AE-B3 all $FF's BRA.L <reserved>
$B4-B9 all $FF's BRA.L <reserved>
$BA-BF all $FF's BRA.L <reserved>
System Patch Area
$C0-16F all $FF's SYSPATCH <reserved>
Table C-1. 332Bug Customization Area (cont'd)
DEFAULT
OFFSET VALUE MNEMONIC DESCRIPTION
Sign On Text Message
$170-1FF SIGNON Text string in SYSCALL .WRITE format.
Default values shown in MASM assembly language format below except "^" has been
substituted for each space character (" ") to show exact spacing. The Motorola copyright must
be preserved.
SIGNON DC.B SIGN$2-SIGN$1 Char. count = $8F
SIGN$1 DC.B $0D,$0A,$0A CR,LF,LF
DC.B '332Bug^Debugger/Diagnostics^-^Version^^1.01' =43 chars
DCB.B 36,$20 Pad to end of line; 79-43= 36.
DC.B $0D,$0A CR,LF
DC.B '^^^^(C)^Copyright^1989^by^Motorola^Inc.'
DCB.B 20,$20 Reserve rest of space.
SIGN$2 EQU *
COMMUNICATION FORMATS
Not all combinations of data bits, parity, and stop bits are valid for the M68332 SCI. Table C-
2 details the legal combinations that can be used when customizing 332Bug.
Table C-2. M68332 SCI Communication Formats
CHARACTER
WIDTH PARITY STOP BIT DESCRIPTION
7 None 1 Invalid port setting
7 None 2
7 Even 1
7 Even 2
7 Odd 1
7 Odd 2
8 None 1
8 None 2
8 Even 1
8 Even 2 Invalid port setting
8 Odd 1
8 Odd 2 Invalid port setting
REV. A CHIP SELECTION SUMMARY
TABLE C-3 covers Rev. A of the M68332BCC Business Card Computer and M68332PFB
Platform Board.
TABLE C-3. Rev. A Chip Selection Summary
SIGNAL BOARD/CHIP DESCRIPTION
CSBOOT = BCC U4 332Bug EPROM
CS0 = BCC U3 write enable for MSB=UPPER=EVEN RAM
CS1 = BCC U2 write enable for LSB=LOWER=ODD RAM
CS2 = PFB U1/U3 read enable for MSB/LSB=BOTH RAMS
CS3 = PFB U1 write enable for LSB=LOWER=ODD RAM
CS4 = PFB U4 read enable for MSB=UPPER=EVEN RAM
CS5 = PFB U2 read enable for LSB=LOWER=ODD RAM
CS6 = PFB U5 chip enable for MC68881/882
CS7 = <unused>
CS8 = PFB ABORT pushbutton autovector
CS9 = <unused>
CS10 = PFB U3 write enable for MSB=UPPER=EVEN RAM
. cut/jump U3-27 from CS4 to CS10 required.
NOTE
U1/U2 = 120 nsec RAM with fast termination.
U2/U4 = ROM laid-out wrong, can only be configured as 120 nsec
RAM.
REV. B CHIP SELECTION SUMMARY
TABLE C-3 covers Rev. B of the M68332BCC Business Card Computer and M68332PFB
Platform Board.
TABLE C-4. Rev. B Chip Selection Summary
SIGNAL BOARD/CHIP DESCRIPTION
CSBOOT = BCC U4 332Bug EPROM
CS0 = BCC U3 write enable for MSB=UPPER=EVEN RAM
CS1 = BCC U2 write enable for LSB=LOWER=ODD RAM
CS2 = BCC U2/U3 read enable for MSB/LSB=BOTH RAMS
CS3 = <unused>
CS4 = PFB ABORT pushbutton autovector
CS5 = PFB U5 chip enable for MC68881/882
. cut/jump U5-J3 from CS2 to CS5 required.
CS6 = PFB U2 read enable for LSB=LOWER=ODD RAM
CS7 = PFB U4 read enable for MSB=UPPER=EVEN RAM
CS8 = PFB U1/U3 read enable for MSB/LSB=BOTH RAMS
CS9 = PFB U1 write enable for LSB=LOWER=ODD RAM
CS10 = PFB U3 write enable for MSB=UPPER=EVEN RAM
NOTE
U1/U2 = 120 nsec RAM with fast termination.
U2/U4 = 250 nsec ROM (or jumper selectable as RAM).
PFB REV. C COMPATIBILITY
PFB Rev. C boards have jumpers (J8 - J13) which when installed, make Rev. C PFB's
compatible with Rev. A PFB boards or Rev. B PFB boards.
TABLE C-5. PFB Rev. C Compatiblity
PFB Rev. C
Jumper Jumpers Jumpers
PFB PFB block not installed for installed for
BOARD REVISION Rev. A Rev. B installed (1) Rev. A Rev. B
BCC Rev. A YES NO NO YES NO
BCC Rev. B NO YES YES NO YES
(1) The default when no jumper block is installed is Rev. B.